In semiconductor device packaging, a lead frame is a substrate supporting the chips, which is made of copper or alloy. The lead frame has the following features: good ductibility, high strength, easy formability, excellent coating performance, good corrosion resistance and anti-oxidization performance, high electrical conductivity and thermal conductivity, good adherence to plastic package, and having heat expansion coefficient close to that of the chips and molding material. The lead frame includes a chip carrier for adhering the chip thereon, and a plurality of pins for connecting the chip to the external of the package; wherein, it is necessary to connect the chips with the pins using various connection technologies such as bond wire, metal plate, ribbon or other conductive material.
The lead frames commonly used at present are manufactured by stamping or etching a metal sheet. Generally, the bonding zones on the lead frame (i.e. the chip carrier and pin of the lead frame) are processed by silver plating in spot, ring or other optional patterns in order to enhance the bondage of gold wires or copper wires and prevent oxidization. In addition, depending on the process of interconnection, non-plated lead frames may also be used, wherein the chip is adhered onto the chip carrier with soft solder, and the chip and pins are connected via aluminum wires.
The following is a manufacturing process in the existing semiconductor packaging technology. FIG. 1A is the structural diagram of semiconductor lead frame 1. It includes a chip carrier 11 for adhering the chip, two pins 12 and 13 for connecting the chip to the external of package. As shown in FIG. 1B, the commonly used method for adhering chips is to dispense adhesive material 14 onto the surface of the chip carrier 11 by adhesive injection; wherein, the adhesive material can be epoxy resin, including conductive or non-conductive epoxy resin formed by adhesive injection. As shown in FIG. 1C, the chip (e.g. IC) 15 is then placed on the chip carrier 11 and adhered on it via the adhesive material 14 then cured, thus finishing the chip adherence. As shown in FIG. 1D, the chip 15 is connected respectively to the pin 12 and pin 13 using several metal wires 16. The metal wires 16 are connected with the chip 15 and the pin 12 and pin 13 respectively using wire bonding. As shown in FIG. 1E, the lead frame 1 is plastically molded, and sealed inside the plastic package 17 to finish the packaging procedure. The chip 15 inside the semiconductor package can be connected with the external component via the pins 12 and 13.
The above procedure for connection of the chip and pins can also be as shown in FIG. 1F, wherein the chip 15 is connected with the pins 12 and 13 using several metal connection plates 18. The metal connection plates 18 are respectively connected with the chip 15 and the pins 12 and 13 using adhesive material (e.g. soldering paste or epoxy resin) formed by adhesive injection. Then, as shown in FIG. 1G, the lead frame 1 is plastically molded, and sealed inside the plastic package 17 to finish the procedure. The chip 15 inside the semiconductor package can be connected with the external component via the pins 12 and 13.
The above procedure for connection of the chip and pin can also be as shown in FIG. 1H, wherein the chip 15 is connected with the pin 12 using the metal wire 16, and the chip 15 is connected with the pin 13 using the metal plate 18. The metal wire 16 is connected with the chip 15 and the pin 12 via wire bonding; while the metal connection plate 18 is connected with the chip 15 and the pin 13 respectively using the adhesive material (e.g. soldering paste or epoxy resin) formed by adhesive injection. Then, as shown in FIG. 1I, the lead frame 1 is plastically molded, and sealed inside the plastic package 17 to finish the procedure. The chip 15 inside the semiconductor package can be connected with external components via the pins 12 and 13.
However, the above semiconductor package manufactured by adhering chip and lead frame as well as connecting chip and pins with adhesive material formed by adhesive injection has the following disadvantages:    1. For a package with certain chip carrier size, if adhesive material (soldering paste or epoxy resin) is formed on the chip carrier by adhesive injection, after the chip is adhered on it, the adhesive material will unavoidable overflow around the chip, which takes up certain space therefore limits the chip size to be smaller than the chip carrier size. This is undesirable especially for power semiconductor device as the power handling capability of a power semiconductor device is usually proportional to the chip size.    2. The method of forming adhesive material (soldering paste or epoxy resin) by adhesive injection on the chip carrier for adhering the chip will cause the formed adhesive material to be uneven in thickness, thus resulting in inclination of the chip adhered on it.    3. Existing process of adhering the chip onto the chip carrier using the soldering paste or epoxy resin as the adhesive material tends to produce very high stress likely to cause the chip to crack.    4. It is required to apply hydrogen or nitrogen to cleanup the residual of the soldering paste on the chip after adhering the chip onto the chip carrier using the soldering paste as the adhesive material.    5. During the process of adhering the chip, if soldering paste or eutectic material is used as adhesive material, higher process operating temperature is required, which causes the lead frame to oxidize quickly.    6. After adhesive injection and placing the chip onto the chip carrier, an offline high temperature curing step is required and the production line efficiency is greatly impaired.    7. The epoxy resin has lower electric conductivity and thermal conductivity. The thickness of the epoxy resin formed by adhesive injection is hard to control and tends to be thicker than necessary leading to higher resistance in both current and heat conduction.
In view of the above, it is very necessary to introduce a new semiconductor package and method, improve the existing chip adherence technology to overcome the disadvantages, thus enhancing product quality and productivity.